The Transistor - The Switch That Built The World

4.0 What this chapter gives you#

1. You will be able to say what a transistor is, in one sentence, without lying.
2. You will understand doping: how a few foreign atoms turn silicon from a poor conductor into a controllable one.
3. You will understand what a “hole” is, and why it behaves like a positive particle.
4. You will be able to explain a PN junction and a diode from first principles.
5. You will know the real history of the 1947 invention, including the argument about credit.
6. You will understand the MOSFET properly: gate, oxide, threshold, inversion, and its two operating regions.
7. You will understand CMOS, and be able to calculate the power a chip burns.
8. You will be able to state Moore’s Law correctly and explain why it was always an economic claim, not a promise about speed.

4.1 Before the transistor: relays and glowing glass#

PLAIN4.1.1 in simple words#

1. A computer needs one thing above all: a switch that another wire can flip.
2. The first such switch was the relay: an electromagnet that pulls a metal arm onto a contact.
3. The next switch was the vacuum tube: a glass bulb with the air pumped out and a hot wire inside.
4. Put a wire mesh in between, and a small voltage on that mesh throttles the flow. A switch with no moving parts.
5. Tubes are about a thousand times faster than relays. They are also hot, fragile, power-hungry, and they die.

PLAIN4.1.2 a picture in your head#

1. A relay is a drawbridge with a motor. A small signal starts the motor, the bridge lowers, and heavy traffic crosses.
2. A vacuum tube is a hose with a valve. The water is already under pressure; your hand on the valve barely works at all.
3. The tube’s valve is a voltage on a mesh. Turning it costs almost nothing, but it controls a large current.
4. Where this comparison breaks: a drawbridge and a valve must physically move. In a tube only electrons move, which is why it is so much faster.
5. And no plumbing picture covers the heater. The tube burns power all the time just to keep electrons boiling off, whether or not it is doing anything.

PLAIN4.1.3 a worked example#

1. Konrad Zuse built the Z3 in Berlin from telephone relays and presented it to an audience of scientists on 12 May 1941.
2. It used about 2,600 relays, roughly 1,400 of them for memory, and ran at about 5 to 10 cycles per second.
3. ENIAC, built from tubes at the University of Pennsylvania, was formally dedicated on 15 February 1946.
4. Its machine cycle was 200 microseconds and it did about 5,000 additions per second.

5. The Z3 itself was destroyed on 21 December 1943 in an Allied bombing raid on Berlin.

PLAIN4.1.4 what is really happening inside#

1. The cathode is metal heated by a filament to roughly 1,000 degrees Celsius. Hot metal throws electrons off its surface.
2. The anode, or plate, sits opposite at a positive voltage, often 100 to 300 volts, so electrons stream across the empty space. That is the current.
3. The grid, a fine mesh, sits in the path. A small negative voltage on it pushes electrons back, thinning the stream.
4. Because the grid is negative, almost no current flows into it. Large plate current, tiny grid current. That is amplification.
5. Now the costs. Every heater runs constantly, so ENIAC drew about 150 kilowatts, much of it just keeping filaments hot.
6. Filaments burn out, because that is physically what they are. And the machine cannot be used the instant you switch it on: cathodes need tens of seconds to reach temperature. That is warm-up time.

TECHNICAL4.1.5 the engineer’s version#

1. John Ambrose Fleming patented the thermionic diode in 1904. Lee de Forest added the control grid in 1906, producing the triode he called the Audion.
2. ENIAC used ordinary octal-base radio tubes: 6SN7 flip-flops in the decimal accumulators, with 6L7, 6SJ7, 6SA7 and 6AC7 types in logic roles.

3. The tube count is quoted differently by different sources. 17,468 is the usual figure for the machine as built. Penn and several standard references round it to 18,000, and the count changed over its working life.
4. Early on, several tubes failed almost every day and ENIAC was unusable roughly half the time. High-reliability tubes arrived in 1948, after which failures dropped to about one every two days.
5. The longest failure-free run was 116 hours, close to five days, in 1954. ENIAC was switched off for the last time on 2 October 1955.
6. The honest version: failures were reduced partly by never switching the machine off. Thermal cycling, not steady running, kills filaments.
7. A 6SN7 heater draws 6.3 V at 0.6 A, about 3.8 W per tube. Multiplied by roughly 17,000 tubes that is about 65 kW of pure heater load, a large share of the 150 kW total.

WORDS4.1.6 remember these#

1. Relay — an electromagnet that flips a metal switch — electromechanical single-pole element with millisecond operate time.
2. Vacuum tube — a glass bulb with a hot wire controlling electron flow — thermionic valve using emission into an evacuated envelope.
3. Triode — a tube with cathode, mesh and plate — three-electrode thermionic device with a control grid.
4. Thermionic emission — hot metal throwing off electrons — thermally activated escape over the material’s work function barrier.
5. Warm-up time — the wait before a tube machine works — the time for indirectly heated cathodes to reach emission temperature, 10 to 60 seconds.

4.2 Doping, properly#

PLAIN4.2.1 in simple words#

1. Pure silicon is a poor conductor: not an insulator, not a metal, something annoying in between.
2. Each silicon atom has four outer electrons, and in a crystal every one is locked into a shared bond with a neighbour.
3. So we cheat. We add a very small number of foreign atoms. This is called doping.
4. Phosphorus and arsenic have five outer electrons. Four join the bonds; the fifth wanders off nearly free. Now there are spare electrons.
5. Silicon doped this way is N-type, N for negative, because the loose carriers are negative electrons.
6. Boron has three outer electrons. It fills three bonds and leaves the fourth with a gap in it.
7. That gap is a hole, and silicon doped this way is P-type.

PLAIN4.2.2 a picture in your head#

1. Picture a cinema where every seat is taken. Nobody can move. That is pure silicon.
2. Make one person stand in the aisle. That is N-type: a free electron that can walk anywhere.
3. Now instead take one person out of a seat in the middle, leaving it empty. That is P-type.
4. Nobody is standing, but the empty seat moves: the person to its left slides over, so the gap travels across the room while each person shifts one place. The empty seat is the hole.
5. It is not a thing. It is an absence. But film only the gap and you would swear a real object was moving, in the opposite direction to the people.
6. Also, holes are genuinely harder to push. In silicon a hole moves at roughly a third the speed of an electron under the same push. Hold on to that; it matters enormously later.

PLAIN4.2.3 a worked example#

1. Silicon has about 5 times 10 to the 22 atoms per cubic centimetre.
2. Now dope it. A typical light doping is 1 times 10 to the 16 dopant atoms per cubic centimetre.
3. Ratio: 1e16 divided by 5e22 is 2 times 10 to the minus 7, which is one dopant atom per five million silicon atoms.
4. But free carriers rise from 1e10 to 1e16. A million times more.

Pure silicon: 5e22 atoms, ~1e10 free electrons -> poor conductor
Add 1e16 P:   5e22 atoms, ~1e16 free electrons -> useful N-type

Dopant to silicon ratio : 1 in 5,000,000
Change in free carriers : about 1,000,000 times

5. One foreign atom in five million changes conductivity by a factor of about a million. The knob is absurdly sensitive.

PLAIN4.2.4 what is really happening inside#

1. A phosphorus atom takes a silicon lattice site. It is a similar size, so the crystal barely notices, and four of its five outer electrons pair with the four silicon neighbours.
2. The fifth is only weakly bound, needing about 0.045 electron-volts to break free. Room temperature heat energy is about 0.026 electron-volts, and given how many attempts happen per second that frees essentially all of them.
3. The freed electron leaves behind a phosphorus atom with one more proton than electron: a fixed positive ion.
4. Boron is the mirror image. It fills three bonds and leaves one incomplete. An electron from a nearby bond hops in to complete it, so the gap moves, and boron becomes a fixed negative ion.
5. So the picture is mobile carriers wandering, and charged ions frozen in place. Section 4.3 depends entirely on that distinction.
6. The honest version: a hole is not a particle. It is the collective behaviour of a nearly full band of electrons, which physics lets us describe exactly as one positive particle with its own effective mass.

TECHNICAL4.2.5 the engineer’s version#

1. Silicon is a group 14 element with an indirect bandgap of 1.12 eV at 300 K and an atomic density of 5.0 times 10 to the 22 per cubic centimetre.
2. Intrinsic carrier concentration ni at 300 K is about 1.0 times 10 to the 10 per cubic centimetre. Older texts quote 1.45e10; the lower value is the modern accepted figure.
3. The mass action law holds in equilibrium: n times p equals ni squared. So N-type doping of 1e16 gives n about 1e16 and p about 1e4 per cubic centimetre.
4. Mobility at 300 K in lightly doped silicon: electrons about 1,400 cm squared per volt-second, holes about 450. A ratio near 3 to 1.

5. Measurement tools: a four-point probe gives sheet resistance in ohms per square; secondary ion mass spectrometry (SIMS) gives the dopant depth profile.
6. Note the convention: N-type and P-type name the majority carrier, not a net charge. Both materials are electrically neutral in bulk.

WORDS4.2.6 remember these#

1. Doping — adding a tiny amount of another element — controlled introduction of substitutional impurities to set carrier concentration.
2. N-type — silicon with spare electrons — donor-doped semiconductor with electrons as majority carrier.
3. P-type — silicon with gaps in its bonds — acceptor-doped semiconductor with holes as majority carrier.
4. Hole — a missing electron that acts positive — an empty valence band state, treated as a quasiparticle of charge plus q.
5. Intrinsic carrier concentration — how conductive pure silicon is — ni, about 1e10 per cubic centimetre at 300 K.

4.3 The PN junction and the diode#

PLAIN4.3.1 in simple words#

1. Take N-type silicon, with spare electrons, and P-type silicon, with holes, and join them as one crystal with the doping changing partway through.
2. Electrons on the N side are crowded and the P side has almost none, so they spill across. Holes spill the other way.
3. That leaves a thin strip near the boundary with no free carriers at all, called the depletion region.
4. But the fixed ions remain, positive on the N side and negative on the P side, so a voltage now exists across that strip. Nobody applied it. It built itself, and it is a barrier to further spilling.
5. Push current one way and the barrier shrinks, so current flows easily. Push the other way and the barrier grows, so almost nothing flows.
6. A device that passes current one way and blocks the other is a diode.

PLAIN4.3.2 a picture in your head#

1. Picture two adjoining rooms at a party with an open doorway. The left room is packed, the right nearly empty.
2. People spill through the doorway, because crowds spread out. That is diffusion. But every person who crosses must hand over their coat at the door, and the coats pile up until crossing stops.
3. The coat pile is the depletion region. It builds itself out of what already crossed, and it is what stops any more crossing.
4. A doorman who pushes people toward the doorway compresses the pile and crossing resumes. That is forward bias.
5. Where this comparison breaks: coats are a passive obstruction, but the depletion region is an electric field, acting instantly and at a distance.

PLAIN4.3.3 a worked example#

1. Take a 1N4148 small-signal silicon diode. Connect its P side (the anode) to plus and its N side (the cathode) to minus. That is forward bias.

2. Look at the pattern. Every extra 60 millivolts multiplies the current by ten. That is not a straight line, it is exponential.
3. Now reverse it. At minus 5 volts you might measure 10 nanoamps. At minus 50 volts, still nanoamps.
4. Forward current at 0.7 V is about 10 milliamps. Reverse current is about 10 nanoamps. A ratio of a million to one.

PLAIN4.3.4 what is really happening inside#

1. At the moment of joining, electrons diffuse into the P side and holes diffuse into the N side.
2. Every electron that leaves the N side leaves a fixed positive donor ion behind, and every hole that leaves the P side leaves a fixed negative acceptor ion. Neither ion can follow.
3. So a wall of positive fixed charge builds on the N side of the boundary and a wall of negative fixed charge on the P side.
4. Separated charge makes an electric field that pushes electrons back toward the N side, exactly opposing the diffusion that created it. Balance is reached when the two cancel, and nothing net flows.
5. The voltage across the region is the built-in potential, typically 0.6 to 0.8 volts in silicon. You cannot measure it with a voltmeter: the two metal-to-silicon contacts produce equal and opposite offsets.
6. Apply an external voltage with the P side positive and the depletion region narrows, the barrier drops, and carriers flood across.
7. Apply the opposite and the region widens, the barrier grows, and majority carriers cannot get over it at all.
8. The honest version: current is not simply blocked one way. Diffusion and drift currents always flow in both directions. Diode current is the small difference between two large, nearly equal opposing flows.

TECHNICAL4.3.5 the engineer’s version#

1. The Shockley diode equation: I = Is times (exp(V divided by (n times VT)) minus 1).
2. VT is the thermal voltage, kT divided by q, equal to 25.85 mV at 300 K. Is is the reverse saturation current, typically 1e-12 to 1e-15 A for small silicon diodes, roughly doubling every 10 K. n is the ideality factor, between 1 and 2.
3. The decade-per-60-mV rule follows directly: 1 times 25.85 mV times 2.303 equals 59.5 mV.
4. Built-in potential is Vbi = VT times ln(Na times Nd divided by ni squared). With Na and Nd both 1e17 and ni equal to 1e10, Vbi = 0.02585 times 32.2, which is 0.83 V.

5. Reverse breakdown has two mechanisms: Zener tunnelling below about 5 V with a negative temperature coefficient, and avalanche multiplication above about 6 V with a positive one. Near 5.6 V they cancel, which is why 5.6 V Zener diodes were once used as temperature-stable references.
6. A Schottky diode is a metal-semiconductor junction with no stored minority charge, so it has essentially no reverse recovery. That is why it dominates high-frequency switching supplies.
7. To observe the curve: a curve tracer or a source measure unit sweep. In simulation, a SPICE DC sweep with the .DC directive plots it from the model parameters IS, N, RS and BV.

WORDS4.3.6 remember these#

1. PN junction — where N-type meets P-type — a metallurgical junction with a self-forming space-charge region.
2. Depletion region — the empty strip at the boundary — space-charge region containing only fixed ionized dopants.
3. Built-in potential — the voltage that appears by itself — Vbi, set by doping levels and ni, about 0.7 V in silicon.
4. Forward bias — pushing the easy way — P side positive, barrier lowered, exponential injection current.
5. Reverse bias — pushing the blocked way — N side positive, barrier raised, only saturation current flows.

4.4 The first transistor, and the argument about it#

PLAIN4.4.1 in simple words#

1. Bell Telephone Laboratories had a business problem in the 1940s. Long distance calls needed amplifiers, amplifiers meant vacuum tubes, and tubes kept dying.
2. On 16 December 1947, two of their people made one work.
3. Their device was a small slab of very pure germanium with two gold contacts pressed onto its surface, extremely close together.
4. A signal on one contact controlled a larger current through the other, amplifying by up to about a hundred times.
5. On 23 December 1947 they demonstrated it to management. Their group leader, William Shockley, called it a magnificent Christmas present.
6. Bell Labs kept it quiet for six months, then announced it at a New York press conference on 30 June 1948.

PLAIN4.4.2 a picture in your head#

1. Imagine controlling a river using only the shape of the riverbed just under the surface, without touching the water.
2. That was the field-effect idea, tried since the 1920s. It kept failing and nobody knew why.
3. Bardeen worked out why in 1947. The semiconductor surface was covered in trapped electrons acting like a shield.
4. So Bardeen and Brattain stopped pushing from outside and went in through the surface directly, with two metal points almost touching.
5. Where this comparison breaks: the point-contact device is not really a field-effect transistor at all, and exactly how it worked was argued about for years afterwards.

PLAIN4.4.3 a worked example#

1. Brattain wrapped gold foil around the point of a small plastic wedge.
2. He cut the foil at the tip with a razor blade, leaving two gold edges about 50 micrometres apart. That is roughly half the width of a human hair.
3. He pressed the wedge onto a slab of high-purity germanium with a spring. One gold edge was the emitter, the other the collector, and the germanium slab itself was the base.
4. They measured a power gain. That is the test that matters; voltage gain alone can be had from a transformer.

PLAIN4.4.4 what is really happening inside#

1. Shockley was the group leader who had pushed the field-effect programme for years, and it had failed repeatedly. The device that finally worked was built by two of his subordinates, using Bardeen’s surface-state insight, in a direction Shockley had not chosen.
2. Then Bell Labs lawyers examined the patent and found Shockley’s own field-effect writing was uncomfortably close to patents Julius Edgar Lilienfeld had filed in the 1920s.
3. To keep the patent safe they left Shockley’s name off it. The application “Three-electrode circuit element utilizing semiconductive materials”, with a priority date of 26 February 1948, named Bardeen and Brattain.
4. Shockley was furious. Over the New Year he worked alone, largely in a Chicago hotel room, and in January 1948 conceived a better device.
5. Instead of two metal points scratching a surface, he proposed a sandwich of three doped layers grown into one crystal: the junction transistor. His own application carries a priority date of 26 June 1948.
6. It was more robust and manufacturable, and it made the point-contact device obsolete. Gordon Teal and Morgan Sparks at Bell Labs produced working grown-junction transistors in 1951. Bardeen left for the University of Illinois that year.
7. In 1956 all three shared the Nobel Prize in Physics, “for their researches on semiconductors and their discovery of the transistor effect.”
8. Where experts disagree: some historians treat Shockley as the essential figure, since the junction transistor is the ancestor of everything since. Others treat him as a manager who claimed a result he did not produce. The safest reading is that invention and improvement both mattered, and came from different people.

TECHNICAL4.4.5 the engineer’s version#

1. The 1947 device was a point-contact transistor on N-type germanium with two gold point contacts about 50 micrometres apart, amplifying the input by up to about 100 times.
2. Germanium, not silicon. Germanium has a 0.66 eV bandgap and much higher carrier mobility, and in 1947 it could be purified far better than silicon.
3. Gordon Teal at Texas Instruments announced the first commercial silicon transistor in 1954. Silicon’s wider 1.12 eV bandgap gives far better high-temperature behaviour.
4. The Regency TR-1, announced on 18 October 1954, was the first commercial transistor radio. It used four TI germanium transistors and sold for $49.95.
5. Shockley left Bell Labs in 1955 and founded Shockley Semiconductor Laboratory in Mountain View, California, in 1956.
6. In 1957 eight of his staff resigned over his management and founded Fairchild Semiconductor. Fairchild’s descendants include Intel and AMD. That is the direct reason Silicon Valley is where it is.
7. John Bardeen won a second Nobel Prize in Physics in 1972, with Leon Cooper and John Robert Schrieffer, for the BCS theory of superconductivity. He remains the only person to have won the physics prize twice.

WORDS4.4.6 remember these#

1. Point-contact transistor — two metal points on a germanium slab — the 1947 device, with emitter and collector point contacts on a base.
2. Surface states — trapped charge that shields the inside — states at a semiconductor surface that pin the Fermi level and screen applied fields.
3. Junction transistor — a sandwich of three doped layers — Shockley’s 1948 bipolar structure, ancestor of the BJT.
4. Power gain — output power larger than input power — the test that separates an amplifier from a transformer.
5. Germanium — the first material that worked — group 14 semiconductor, 0.66 eV bandgap, superseded by silicon for thermal reasons.

4.5 The bipolar junction transistor#

PLAIN4.5.1 in simple words#

1. Take three doped layers in a row: N, then P, then N. That is an NPN transistor. Reverse every layer and you have a PNP.
2. The base is deliberately made very thin and only lightly doped. That is the whole secret.
3. Feed a small current into the base and a much larger current flows from collector to emitter, typically 100 to 300 times larger.
4. There is a catch, and it is the catch that killed this device for computing.
5. Base current means power burned. Millions of these would burn power constantly, even doing nothing.

PLAIN4.5.2 a picture in your head#

1. Picture a wide fast river with a narrow island in the middle.
2. Water hitting the island drains away down a small side channel. That side channel is the base current.
3. Because the island is so narrow, almost all the water sweeps past it and reaches the far bank. Maybe two hundred litres arrive for every one that drains.
4. But the side channel must keep draining. Block it and the whole flow stops.
5. And the small side flow is never optional. It is a permanent cost, and section 4.7 is about a device that removed it.

PLAIN4.5.3 a worked example#

1. Take a 2N3904, one of the most common small NPN transistors ever made. Its current gain, beta, is roughly 100 to 300 at 10 milliamps.
2. Say we want to switch a 100 milliamp load. Use the worst-case beta of 100, never the typical value, so base current needed = 100 mA divided by 100 = 1 mA.
3. In practice you overdrive by 5 times to force it hard on, so use 5 mA.
4. With a 5 V control signal, the base-emitter junction drops about 0.7 V, so the resistor sees 4.3 V, and R = 4.3 V divided by 0.005 A = 860 ohms. Use the standard value 820 ohms.

   5V ---[820 ohm]--- base
                       |
   100 mA load ---> collector
                       |
                    emitter --- ground

   Base power  : 5 mA x 0.7 V   = 3.5 mW
   Switch loss : 100 mA x 0.2 V = 20 mW
   Total burnt : about 23.5 mW, continuously

5. Holding this one transistor on costs about 23.5 milliwatts forever, doing nothing.
6. A billion of them would burn 23.5 megawatts. That is a power station, and that number is why bipolar logic was never going to build a modern processor.

PLAIN4.5.4 what is really happening inside#

1. In an NPN the emitter is heavily doped, the base thin and lightly doped, and the collector moderately doped and physically larger.
2. Forward bias lowers the emitter-base barrier, so electrons flood from the N emitter into the P base, where they are minority carriers and ought to recombine.
3. But the base is thinner than a micrometre, so most cross it before meeting a hole, and at the far edge the reverse-biased base-collector field sweeps them straight into the collector.
4. So perhaps 99.5 percent arrive at the collector and 0.5 percent recombine in the base and must be replaced by base current.
5. Beta is just the ratio of those two numbers. Lose 0.5 percent and beta is about 200. Gain comes from geometry and doping, not magic.
6. Cut-off is when base-emitter voltage is below about 0.6 V. Nothing is injected and the device is off.
7. The honest version: calling the BJT current-controlled is a convention, not a law. The physics is exponentially controlled by base-emitter voltage. But that exponential is so steep and so temperature-sensitive that designing with base current is far more reliable, so everyone does.

TECHNICAL4.5.5 the engineer’s version#

1. The Ebers-Moll model describes the BJT. In forward active mode IC = Is times exp(VBE divided by VT).
2. Common-emitter gain beta equals IC over IB. Common-base gain alpha equals IC over IE. They relate as beta = alpha divided by (1 minus alpha).

3. Bipolar logic families ran RTL, then DTL, then TTL. The 7400 series launched by Texas Instruments in 1964 and dominated digital design for twenty years.
4. Standard TTL dissipated roughly 10 mW per gate at rest; the 74LS low-power Schottky family reduced this to about 2 mW. Emitter-coupled logic was faster still at 25 mW or more per gate, and Cray supercomputers cooled it with liquid.
5. Bipolar devices still dominate analogue and radio work: low noise, high transconductance per unit current, excellent matching. They lost digital, not everything. Silicon-germanium heterojunction bipolar transistors reach fT above 300 GHz.
6. SPICE models BJTs with the Gummel-Poon model, which extends Ebers-Moll to cover high injection and base-width modulation.

WORDS4.5.6 remember these#

1. BJT — a sandwich transistor controlled by current — bipolar junction transistor, using both electrons and holes as carriers.
2. Emitter — the layer that supplies carriers — heavily doped terminal that injects minority carriers into the base.
3. Base — the thin middle layer that controls things — lightly doped region, thinner than the minority carrier diffusion length.
4. Collector — the layer that catches carriers — reverse-biased terminal that sweeps arriving minority carriers out.
5. Beta or hFE — how many times the current is multiplied — common-emitter DC current gain, IC over IB, typically 20 to 500.

4.6 The MOSFET, the transistor inside your computer#

PLAIN4.6.1 in simple words#

1. Almost every transistor in the device you are reading this on is a MOSFET.
2. It has three parts you must know. The source, where carriers come from. The drain, where they go. The gate, which decides whether they go.
3. Because the gate is insulated, no current flows into it. It is a capacitor plate, not a wire into the device.
4. Put a positive voltage on the gate of an N-channel MOSFET and its electric field reaches through the insulator into the silicon below.
5. That field drags electrons up to the surface, forming a thin conducting layer bridging source to drain. That layer is the channel.
6. Here is the point that changes everything. Because the gate is insulated, holding the switch on costs no continuing current. You charge the gate once and it stays.

PLAIN4.6.2 a picture in your head#

1. Imagine a dry canal between two full reservoirs. Nothing can cross.
2. Lower the plate and it does not push water. Instead it pulls groundwater up from below, filling the canal bed.
3. That is the gate, and that is why MOSFET logic can sit still without burning power.
4. Where this comparison breaks: lowering a real plate costs energy each time because of gravity, and so does switching a real gate, because its capacitance must be charged and discharged. Holding is free; changing is not.
5. Also, the insulator is not perfect. At modern thicknesses a few electrons tunnel straight through. The plate leaks, slightly.

PLAIN4.6.3 a worked example#

1. Here is a planar N-channel MOSFET, sliced through the middle.

        source          gate           drain
          |              |               |
        +-v--+   +-------v-------+   +---v--+
        |    |   |  gate metal   |   |      |
        |    |   +---------------+   |      |
        |    |   |  gate oxide   |   |      |
  +-----+----+---+---------------+---+------+----+
  |     |  N+    | ==== channel ==== |   N+      |
  |     +--------+-------------------+-----------+
  |            P-type body (substrate)           |
  +----------------------------------------------+
                        |
                       body

2. The channel is the dashed strip. It does not exist until the gate says so.
3. Now real numbers. Threshold voltage, the gate voltage at which the channel appears: 0.4 V. Supply: 1.0 V. Channel length L: 20 nanometres. Channel width W: 100 nanometres.
4. Below 0.4 V on the gate the device is off, passing only leakage.
5. At 1.0 V on the gate the overdrive is 1.0 minus 0.4, which is 0.6 V, and the device is fully on.
6. Double the width to 200 nanometres and on-current doubles, because a wider channel is a wider pipe.
7. Halve the length to 10 nanometres and on-current doubles too, because a shorter pipe has less resistance.
8. That is why engineers speak of the W over L ratio. It is the shape knob for strength.

PLAIN4.6.4 what is really happening inside#

1. Start with the gate at zero volts, on an N-channel device built in P-type silicon. The body is full of holes and the two N+ islands are full of electrons.
2. Source to body is one PN junction and body to drain is another, facing the other way. Two back-to-back diodes cannot conduct either direction, so the device is firmly off.
3. Raise the gate a little. The field pushes holes downward, away from the surface, which is now depleted: no holes, no electrons. Still off, but the barrier is thinning.
4. Raise the gate more and the field starts pulling electrons up to the surface. Electrons in P-type silicon are minority carriers and very rare, but the field only needs a thin layer.
5. At some gate voltage the electron count at the surface equals the hole count in the bulk. That point is the threshold voltage.
6. Push past it and electrons outnumber holes at the surface. The surface has stopped behaving as P-type and started behaving as N-type.
7. That flip is called inversion, and it is the heart of the device. The material did not change. Its carrier population did.
8. Now source, channel and drain are all N-type. One continuous path. Current flows, and what happens next depends on the drain voltage.
9. If drain voltage is small, the channel is roughly even from end to end and the device behaves as a resistor whose value the gate sets. That is the linear or triode region.
10. Raise drain voltage and the channel is squeezed at the drain end, because the gate-to-channel voltage there is smaller. When its thickness there reaches zero, the device has reached pinch-off.
11. Past that, raising drain voltage barely raises current. The device behaves as a current source set by the gate. That is the saturation region.
12. Careful, this word is a trap. In a BJT, saturation means fully on with the lowest voltage drop. In a MOSFET it means pinched off at constant current. Same word, opposite feeling.
13. A PMOS device is the mirror image: P+ source and drain in an N-type well, turned on by a negative gate voltage relative to the source, which inverts the surface to P-type.
14. The honest version: “the channel disappears at pinch-off” is not quite true. A thin high-field region forms at the drain end and carriers are swept across it. Current does not stop, it stops increasing.

TECHNICAL4.6.5 the engineer’s version#

1. Julius Edgar Lilienfeld filed the first field-effect patents in the mid 1920s and Oskar Heil filed a British patent in 1934. Neither produced a working device.
2. Shockley’s 1945 field-effect attempts failed. Bardeen’s 1947 surface state theory explained why: interface traps pinned the Fermi level and screened the applied field.
3. The solution was a clean thermally grown silicon dioxide interface. Mohamed Atalla and Dawon Kahng at Bell Labs built the first working MOSFET in 1959 and reported it in 1960.
4. Linear region, long-channel model: ID = mu times Cox times (W over L) times ((VGS minus Vth) times VDS minus VDS squared over 2), for VDS below VGS minus Vth.
5. Saturation region, long-channel model: ID = one half times mu times Cox times (W over L) times (VGS minus Vth) squared, for VDS at or above VGS minus Vth. Cox is gate oxide capacitance per unit area, the oxide permittivity divided by oxide thickness tox.
6. The square law is a long-channel result. Modern short-channel devices are velocity saturated, so drain current is close to linear in (VGS minus Vth), not quadratic. Textbooks teaching only the square law are teaching a device that stopped being manufactured decades ago.
7. Below threshold the device is not off. Subthreshold current falls exponentially, at a rate called subthreshold swing S, in millivolts per decade.
8. S has a hard floor of ln(10) times kT over q, which is 59.6 mV per decade at 300 K. Real planar devices reach 70 to 100; FinFETs reach about 65 to 70.
9. That floor is thermodynamic, not an engineering limit. It is the single biggest reason supply voltage stopped scaling, and therefore the reason for the power wall in section 4.10.
10. Intel reported reaching 1.2 nm of silicon dioxide, about five atomic layers, on its 65 nm process. Below that, direct tunnelling leakage became intolerable.

WORDS4.6.6 remember these#

1. MOSFET — a switch controlled by a voltage on an insulated plate — metal oxide semiconductor field-effect transistor, a unipolar device.
2. Source and drain — where carriers come from and go to — heavily doped regions of opposite type to the body.
3. Gate — the insulated control plate — electrode capacitively coupled to the channel, drawing only tunnelling leakage.
4. Gate oxide — the thin insulator under the gate — dielectric layer, silicon dioxide historically, hafnium-based high-k since 2007.
5. Threshold voltage — the gate voltage where it switches on — Vth, the point of strong inversion at the semiconductor surface.
6. Channel — the conducting bridge the gate creates — inversion layer of minority carriers at the oxide interface.
7. NMOS and PMOS — the electron version and the hole version — N-channel and P-channel devices, on with positive and negative gate overdrive.

4.7 CMOS: the pairing that made low power possible#

PLAIN4.7.1 in simple words#

1. One MOSFET alone still wastes power. Pull a signal low through a resistor and current keeps flowing through that resistor.
2. Put a PMOS on top connected to the supply, and an NMOS below connected to ground. Join their gates and join their drains.
3. Feed in a 0. The PMOS turns on, the NMOS turns off, and the output is pulled up to the supply, a 1.
4. In both steady states exactly one transistor is on, so there is never a path from supply to ground. No path means no current.
5. CMOS stands for Complementary Metal Oxide Semiconductor. Complementary means the two types are used as a matched opposing pair.

PLAIN4.7.2 a picture in your head#

1. Think of a sink with a tap above and a plug below, joined by one lever.
2. Push the lever one way and the tap opens while the plug closes, so the basin fills.
3. The mechanism guarantees tap and plug are never open together, so water never runs straight down the drain.
4. Where this comparison breaks: during the flick of the lever both really are slightly open for an instant. That overlap is called crowbar or short-circuit current, and it is a real cost in fast circuits.

PLAIN4.7.3 a worked example#

1. Here is the CMOS inverter as a circuit.

              VDD  (the supply, logic 1)
               |
          +----+----+
   IN ----|  PMOS   |   on when IN is 0
          +----+----+
               |
               +-------------> OUT
               |
          +----+----+
   IN ----|  NMOS   |   on when IN is 1
          +----+----+
               |
              GND  (ground, logic 0)

   IN = 0 -> PMOS on, NMOS off -> OUT pulled to VDD = 1
   IN = 1 -> PMOS off, NMOS on -> OUT pulled to GND = 0

2. Now calculate the power a real chip burns. The formula is P = alpha times C times V squared times f.
3. C is the capacitance being charged, V the supply voltage, f the clock frequency, and alpha the activity factor, the fraction of nodes that change on a given tick.
4. Take a plausible processor core cluster: one billion switching nodes, 0.5 femtofarads each, 1.0 V supply, 3 GHz clock, activity factor 0.05.
5. Capacitance switched per cycle = 0.05 times 1e9 times 0.5e-15 farads = 2.5 times 10 to the minus 8 farads, that is 25 nanofarads.
6. Energy per cycle = C times V squared = 25 nF times 1.0 squared = 25 nanojoules.
7. Power = 25 nanojoules times 3 billion cycles per second = 75 watts.
8. Now change one number. Raise the supply to 1.2 V and power scales with V squared: 75 times 1.44 = 108 watts, for zero extra speed.

PLAIN4.7.4 what is really happening inside#

1. When the input flips from 1 to 0, the PMOS turns on and connects the output wire to the supply.
2. That output wire, plus the gates of everything it drives, forms a capacitance that must be charged from 0 volts up to the supply voltage.
3. Charging a capacitor C to voltage V stores one half C V squared and burns the same amount as heat in the transistor doing the charging. On the way back, the NMOS dumps the stored half to ground and that is lost too.
4. So a full 0 to 1 to 0 cycle costs C times V squared in total. That is where the formula comes from. Nothing at all is spent while the output sits still, which is the property bipolar logic could never offer.
5. Two other losses exist. First, crowbar loss: for the moment when the input is halfway, both transistors conduct and a spike passes through.
6. Second, and worse, leakage. Every off transistor passes a small current, and every gate leaks a tunnelling current through its oxide.
7. In the 1990s leakage was negligible. By the 90 nanometre generation, around 2003 to 2005, it had become a large share of total chip power.

TECHNICAL4.7.5 the engineer’s version#

1. CMOS was invented by Frank Wanlass and Chih-Tang Sah at Fairchild in 1963. Their ISSCC paper described it as “nanowatt logic”.
2. US patent 3,356,858 was filed 18 June 1963 and issued 5 December 1967. RCA shipped the CD4000 logic family in 1968.
3. Dynamic power: P_dyn = alpha times C_L times VDD squared times f. Static power: P_static = VDD times I_leak, summed over every device. Short-circuit power is typically 5 to 15 percent of dynamic power.
4. Leakage components are subthreshold conduction, gate oxide tunnelling, junction band-to-band tunnelling, and gate-induced drain leakage (GIDL).
5. Subthreshold leakage rises exponentially as threshold voltage falls, at roughly one decade per S millivolts, with S about 70 mV per decade.

6. Mitigations in current use: high-k metal gate from Intel’s 45 nm in 2007, multi-threshold cell libraries, power gating with sleep transistors, clock gating, dynamic voltage and frequency scaling, and FinFET or nanosheet geometry for better electrostatic control.
7. Why clocks stopped climbing: Intel’s Pentium 4 Prescott reached 3.8 GHz in November 2004 and stopped there.
8. In May 2004 Intel cancelled the Tejas and Jayhawk projects, which had aimed at much higher clock rates, and redirected to dual-core designs. The first dual-core desktop part, the Pentium D, shipped in May 2005.
9. The reason is arithmetic. Raising frequency requires raising voltage to keep timing closed, and power then rises with roughly the cube of frequency.
10. Two cores at 3 GHz do more total work than one core at 4.5 GHz for less power, provided the software can use them. That proviso is the entire subject of parallel programming.
11. Top desktop parts in 2025 boost to roughly 5.7 to 6.0 GHz, about 1.5 times the 2004 peak across twenty years. In the twenty years before 2004, clock rates rose more than a thousand times.

# read package energy counter, microjoules, Intel RAPL
cat /sys/class/powercap/intel-rapl:0/energy_uj

# per-core frequency, temperature and package watts
sudo turbostat --interval 1

WORDS4.7.6 remember these#

1. CMOS — using an N and a P transistor as an opposing pair — complementary MOS logic with no static path from supply to ground.
2. Inverter — the gate that flips 0 to 1 — series PMOS pull-up and NMOS pull-down sharing gate and drain nodes.
3. Dynamic power — the cost of changing — alpha C V squared f, paid per transition.
4. Static power — the cost of merely existing — VDD times total leakage current, paid continuously.
5. Activity factor — how often a wire actually changes — alpha, typically 0.01 to 0.2 in real designs.

4.8 The same device, two jobs#

PLAIN4.8.1 in simple words#

1. A transistor does not know whether it is in a computer or a radio. It is the same device doing the same thing.
2. Digital circuits use only the two extremes: fully off and fully on.
3. In between is a region where a small input change makes a large output change. Analogue circuits live there.
4. Digital design crosses that middle region as fast as possible, because it wastes power and its output is undefined.
5. Analogue design treats the same region as the whole point, because that is where gain comes from.

PLAIN4.8.2 a picture in your head#

1. Think of a light switch versus a dimmer knob.
2. A light switch has two positions and you flip past the middle quickly. That is digital.
3. A dimmer sits deliberately in the middle, where a small turn makes a noticeable change. That is analogue.
4. Where this comparison breaks: a mechanical dimmer wastes heat in proportion to how much it dims, and so does a transistor in its middle region, because it is dropping voltage while passing current.
5. That is why a class A audio amplifier is warm with no music playing, and why digital chips never sit in the middle if they can help it.

PLAIN4.8.3 a worked example#

1. The transfer curve plots output voltage against input voltage for one CMOS inverter. Read it left to right.

2. At 0 V in, the NMOS is off and the PMOS fully on, so the output sits at the full supply and the curve is flat. At about 0.5 V, the switching point, it plunges almost vertically to near 0 V, then flattens again.
3. So the curve is flat, then a cliff, then flat again.
4. Digital design wants the two flat ends. Flat means a sloppy input still gives a clean output. That property is noise margin, and it is why digital signals can be copied endlessly without decay.
5. Analogue design wants the cliff. Its slope is the voltage gain, often 20 to 50 for a simple CMOS inverter.
6. Bias an inverter at its switching point with a feedback resistor and you have an amplifier, not a logic gate. This is a real technique, used in crystal oscillator circuits.

PLAIN4.8.4 what is really happening inside#

1. In the flat regions one transistor is in its linear region acting as a small resistance and the other is fully cut off.
2. Almost the full supply appears across the off device and almost none across the on device, so current is essentially zero and so is power.
3. In the cliff region both devices are in saturation, acting as current sources. Two opposing current sources fight, and the output swings wildly for a small input nudge.
4. That is where gain comes from. It is not amplification of energy. The energy comes from the supply, and the transistor is a valve deciding how much of it reaches the output.
5. In the cliff region there is a real path from supply to ground, so current flows and heat is produced. Digital circuits cross that region in tens of picoseconds; analogue circuits sit in it and pay for it in heat.
6. The honest version: a transistor never amplifies power in the sense of creating it. It modulates a large power flow using a small one. Gain is a ratio of signals, never a violation of energy conservation.

TECHNICAL4.8.5 the engineer’s version#

1. Small-signal voltage gain of a CMOS inverter at its switching threshold is minus (gm_n plus gm_p) times (ro_n in parallel with ro_p).
2. Intrinsic gain gm times ro for a single modern short-channel device is only about 10 to 30, and it has fallen as nodes shrank. That is why analogue design got harder, not easier, with scaling.
3. Noise margins: NMH = VOH minus VIH, and NML = VIL minus VOL. For standard CMOS at 5 V, VIH is 3.5 V, VIL is 1.5 V, VOH is 4.9 V and VOL is 0.1 V, giving margins near 1.4 V each way.
4. Radio front ends still commonly use bipolar or silicon-germanium devices for low-noise amplifiers, because their transconductance per unit current and their noise behaviour beat CMOS at the same power.
5. Where experts disagree: whether analogue functions should share the same advanced node as the digital logic. Integration saves packaging and interconnect; separate older nodes give better analogue devices and lower cost. Chiplet packaging has shifted this argument, not settled it.

WORDS4.8.6 remember these#

1. Transfer curve — the plot of output against input — DC voltage transfer characteristic, flat at both ends with a steep transition.
2. Noise margin — how much interference a signal can take — the voltage gap between guaranteed output levels and required input levels.
3. Gain — how much bigger the output change is — the slope of the transfer curve at the operating point.
4. Bias — where you park the device on the curve — the DC operating point set before any signal is applied.
5. Class A — an amplifier that conducts all the time — conduction over the full 360 degrees of the input cycle, at most 50 percent efficient.

4.9 The changing shape of the transistor#

PLAIN4.9.1 in simple words#

1. For about forty years transistors were flat. The channel lay along the top surface of the wafer with the gate above it. That is a planar transistor.
2. As transistors shrank, the flat design began to fail in a specific way. The gate could only touch the channel from one side, the top, while the drain, sitting right next to a very short channel, started to influence it too.
3. So the gate lost the argument. It could no longer switch the channel fully off, and leakage rose sharply.
4. The fix was to change the shape: stand the channel up as a thin vertical fin and wrap the gate around three of its sides. That is a FinFET.
5. The next step wraps the gate around all four sides, making the channel a stack of thin horizontal ribbons with gate material threaded between them.
6. That is gate-all-around, also called nanosheet, and it is the current leading-edge shape.

PLAIN4.9.2 a picture in your head#

1. Imagine stopping water in a pipe by pressing with one hand from above.
2. Now use both hands and a thumb underneath. Three points of grip, much better control.
3. Now imagine a ring clamp closing all the way around. Total control from every direction.
4. Where this comparison breaks: the gate never squeezes anything. It only produces an electric field. But “surrounding it more completely gives more control” is exactly right.

PLAIN4.9.3 a worked example#

1. Here is the timeline of the shape change, with companies and years.

2. Intel announced its 22 nanometre Tri-Gate process on 4 May 2011 and shipped Ivy Bridge processors using it in April 2012. That was the first high-volume FinFET product.
3. Samsung began production with 3 nanometre gate-all-around, marketed as MBCFET, in June 2022.
4. TSMC’s N2 process entered volume production in the fourth quarter of 2025. It is TSMC’s first gate-all-around node.

PLAIN4.9.4 what is really happening inside#

1. The problem the shape solves has a name: short-channel effects.
2. When the channel is long, the gate alone sets the barrier between source and drain. When it is very short, the drain’s own depletion region reaches close to the source.
3. Now raising the drain voltage lowers the source barrier by itself, with no help from the gate. That is drain-induced barrier lowering, or DIBL.
4. Wrapping the gate around more of the channel restores its authority, because the gate’s field now dominates from several directions at once.
5. The results are all bad: threshold voltage drops as the channel shortens, the subthreshold slope degrades so turn-off is less sharp, and off current rises.
6. Silicon-on-insulator, or SOI, attacks a related problem differently. A buried layer of oxide sits under the whole device, cutting off deep leakage paths through the substrate, reducing junction capacitance, and removing the latch-up failure mode entirely.
7. The gate insulator changed too, for a hard physical reason. Silicon dioxide was thinned generation after generation to keep the gate’s grip strong, and Intel reached 1.2 nanometres of it, about five atomic layers, at 65 nanometres.
8. Five atoms is not a film any more. Electrons tunnel straight through it and leakage explodes.
9. The escape was a material with a higher dielectric constant, called high-k, which can be physically thicker while giving the same electrical coupling. Thicker means far less tunnelling.
10. Hafnium-based oxides have a dielectric constant around 20 to 25 against 3.9 for silicon dioxide, which buys back several atomic layers of thickness.
11. High-k films do not work with polysilicon gates, so metal gates had to return at the same time. Hence the paired name, high-k metal gate.

TECHNICAL4.9.5 the engineer’s version#

1. Intel introduced high-k metal gate at 45 nanometres in 2007 with the Penryn family. Gordon Moore called it the biggest change to transistor technology since the polysilicon gate in the late 1960s.
2. Intel’s published figures for that change: gate oxide leakage reduced more than 10 times, source-to-drain leakage more than 5 times, and drive current improved by more than 20 percent.
3. Equivalent oxide thickness (EOT) is the standard figure of merit: the thickness of silicon dioxide that would give the same capacitance per area. Modern EOT is around 0.8 to 1.0 nanometres, at a physical thickness of 2 to 3 nanometres.
4. FinFET geometry parameters are fin height, fin width (typically 5 to 8 nm) and fin pitch (roughly 24 to 30 nm at recent nodes).
5. FinFET width is quantized. You cannot ask for 1.5 fins, so device strength comes in integer multiples of one fin. That constrains circuit design in a way planar devices never did. Nanosheet removes the quantization, because sheet width is drawn continuously.
6. FD-SOI, fully depleted silicon-on-insulator, is a live alternative at 22 nanometres and below, offered by GlobalFoundries as 22FDX. It allows back-bias tuning of threshold voltage at runtime, which FinFET cannot do.
7. Where experts disagree: whether FD-SOI or FinFET suits low-power and radio products at moderate nodes. FinFET won the leading edge outright; FD-SOI retains real advocates for internet-of-things and automotive parts.
8. Beyond nanosheet, the announced direction is CFET, stacking an NMOS device directly on a PMOS device. As of 2026 that is active research and pathfinding, not production.

WORDS4.9.6 remember these#

1. Planar transistor — the old flat design — channel in the wafer surface with a gate above it on one side only.
2. FinFET — a channel on edge with the gate around three sides — tri-gate device with width quantized in integer fins.
3. Gate-all-around — gate wrapped completely around the channel — nanosheet or nanowire device, marketed as MBCFET by Samsung and RibbonFET by Intel.
4. Short-channel effects — the gate losing control as things shrink — DIBL, threshold roll-off, punch-through, subthreshold slope degradation.
5. SOI — a buried insulating layer under the devices — silicon-on-insulator, cutting substrate leakage, junction capacitance and latch-up.

4.10 Scale, Moore’s Law, and the power wall#

PLAIN4.10.1 in simple words#

1. A silicon atom is about 0.22 nanometres across, so a gate insulator one nanometre thick is four or five atoms.
2. In 1971 the Intel 4004 held 2,250 transistors. In 2024 the Apple M4 held about 28 billion. That is a factor of over twelve million in fifty-three years.
3. Moore’s Law is the name for that trend. It is not a law of physics. It is an observation about industry that turned into a plan.
4. It is also not about speed, despite what almost everyone says.
5. It has been slowing since around 2015. Doubling now takes closer to three years than two, and each step costs far more than the last.

PLAIN4.10.2 a picture in your head#

1. Imagine a printing press that gets twice as good every two years, so a page holds twice as many words. For decades each new press also printed faster and used no more electricity. Better in every direction, free.
2. Then something changed. The presses kept holding more words but stopped getting faster, and started running hot.
3. That is exactly what happened to processors around 2005. Cores multiplied because clock speed could not rise.
4. Where this comparison breaks: printing more pages in parallel always helps, but computing in parallel only helps if the task can be split. Many cannot. That limit is called Amdahl’s Law and it is not going away.

PLAIN4.10.3 a worked example#

1. Here is the transistor count table, with real parts and real years.

2. Now count switching events. Take the Apple M4: 28 billion transistors, a 4 GHz clock, and an activity factor of 5 percent.
3. 28e9 times 4e9 = 1.12 times 10 to the 20. Times 0.05 gives 5.6 times 10 to the 18 switching events every second.
4. That is 5.6 billion billion switches per second, in a chip you can cover with a thumb, drawing a few tens of watts.
5. The industry as a whole made about 250 times 10 to the 18 transistors in 2014, according to an IEEE Spectrum estimate. That is roughly 8 trillion transistors manufactured every second of that year.

PLAIN4.10.4 what is really happening inside#

1. Gordon Moore, then at Fairchild, wrote an article for Electronics magazine published on 19 April 1965, titled “Cramming more components onto integrated circuits”.
2. His actual observation: the complexity for minimum component costs had increased at a rate of roughly a factor of two per year, and he expected that to continue for at least ten more years.
3. Read that carefully. “Complexity for minimum component costs” means the number of components on the chip that is cheapest per component.
4. In 1975, at the IEEE International Electron Devices Meeting, Moore revised it: doubling yearly until about 1980, then slowing to about every two years.
5. The “every 18 months” version everyone quotes is not Moore’s. David House, an Intel executive, said in 1975 that more transistors plus faster ones would double performance about every 18 months.
6. Now the second law, the one that actually stopped. Robert Dennard and colleagues at IBM published a 1974 paper on designing ion-implanted MOSFETs with very small physical dimensions.
7. Their scaling rules: shrink every dimension by a factor k, shrink the supply voltage by k, and raise the doping by k.
8. The consequences are beautiful. Area falls by k squared, delay falls by k, power per device falls by k squared, and power per unit area stays constant.
9. Constant power density is the magic line. It means you can double the transistor count, run them faster, and the chip does not get hotter.
10. For roughly thirty years that held, and engineers came to treat it as normal. It was not normal. It was a gift.
11. It ended because supply voltage could not keep falling. Supply voltage must stay well above threshold voltage, and threshold voltage cannot fall without subthreshold leakage rising exponentially.
12. Section 4.6 gave the reason: the 59.6 millivolt per decade thermal floor. That is physics, at any temperature above absolute zero. So voltage stalled near 1 volt around 2005, having fallen from 5 volts.
13. Transistors kept shrinking, but the V squared term stopped shrinking.
14. Power density therefore began to climb. That is the power wall.
15. The industry’s answer was to stop raising clock speed, add cores, and leave large parts of the chip powered down at any moment. That last practice has a name: dark silicon.

TECHNICAL4.10.5 the engineer’s version#

1. Dennard constant-field scaling, with factor k greater than 1: dimensions divided by k, voltage divided by k, doping times k, current divided by k, capacitance divided by k, delay divided by k, power per device divided by k squared, power density unchanged.
2. Post-Dennard reality since roughly 2005: dimensions still divided by k, but voltage nearly constant, so power density rises by roughly k squared.
3. Node names are marketing, not measurements. This is a convention, not a standard. No physical feature on a “3 nm” process measures 3 nanometres.
4. The meaningful density metrics are contacted poly pitch (CPP), metal 1 pitch and cell height in track count. Leading nodes in 2025 sit around 45 to 50 nm CPP and 20 to 24 nm minimum metal pitch. Transistor density is quoted around 200 to 300 million per square millimetre.

5. Interconnect is the underrated one. Copper resistivity rises sharply as wire cross-sections approach the electron mean free path, so wire delay has scaled far worse than transistor delay.
6. Where experts disagree, sharply: whether cost per transistor still falls at the leading edge. Foundries state that it does. Several analysts argue it has been roughly flat since the 28 nanometre node. Nvidia’s chief executive said publicly in 2022 that Moore’s Law is dead. The honest answer is that it depends on volume, yield and which costs you count.
7. Established fact: transistor counts per chip are still rising. Active research: CFET stacking, two-dimensional channel materials such as molybdenum disulphide, and backside power delivery. Marketing claim: any specific node name, and any single number offered as “the density”.
8. Tools to observe scale in practice: lscpu and /proc/cpuinfo on Linux for core and cache topology, and hwloc-ls for the physical layout.

# core count, cache sizes and topology
lscpu

# hierarchical view of packages, cores and caches
hwloc-ls

WORDS4.10.6 remember these#

1. Moore’s Law — chips roughly double in transistor count every two years — an economic observation about components at minimum cost per component.
2. Dennard scaling — shrinking used to make chips faster and no hotter — constant-field scaling giving constant power density per unit area.
3. Power wall — the point where you cannot cool it any faster — the limit reached when power density stopped being constant under scaling.
4. Dark silicon — parts of the chip that must stay off — the fraction of a die that cannot be powered at once within the thermal budget.
5. Process node — the name of a manufacturing generation — a marketing label since roughly 2011, not a measurement of any feature.

4.11 What a transistor costs#

PLAIN4.11.1 in simple words#

1. The most important number about the transistor is not its size or its speed. It is its price.
2. In the mid 1950s one transistor cost a few dollars. You counted them individually and designed circuits to use as few as possible.
3. Today a single dollar buys hundreds of millions of them.
4. That is a fall of roughly a billion times, and it is the reason every other chapter of this book is possible.
5. Caches, branch predictors, graphics units, encryption engines and neural accelerators all exist because transistors became too cheap to ration.

PLAIN4.11.2 a picture in your head#

1. Imagine paper cost as much as gold. You would write only what mattered, on both sides, in tiny letters.
2. Now imagine paper becomes free. You print drafts, take notes you never read, and keep three copies of everything.
3. Where this comparison breaks: transistors are not free, only individually cheap. A leading-edge chip design still costs hundreds of millions of dollars to bring to market.
4. The cost simply moved. It moved off the individual component and onto the design, the masks and the factory.

PLAIN4.11.3 a worked example#

1. Here are real price points across seventy years, as quoted at the time and not adjusted for inflation.

2. Work the modern number. Take a chip with 28 billion transistors whose finished die costs, say, 80 dollars to make.
3. 80 dollars divided by 28 billion is about 2.9 times 10 to the minus 9 dollars per transistor, roughly three billionths of a dollar.
4. Compared with about 1 dollar in 1960, that is a ratio of about 350 million to one.
5. In 1954 the Regency TR-1 pocket radio, announced on 18 October 1954, sold for $49.95 and contained four transistors.

PLAIN4.11.4 what is really happening inside#

1. The price collapse comes from one structural fact: cost scales with wafer area, not with transistor count.
2. Processing a wafer costs roughly the same whether the features on it are large or small. The steps are the same steps.
3. So halving the linear dimension fits four times as many transistors on the same wafer for nearly the same processing cost. That is the true engine of Moore’s Law, and why Moore framed his observation in terms of cost per component.
4. Yield modifies this. A wafer has a certain number of defects, and a bigger die catches more of them, so bigger dies yield worse and not linearly. That is why the industry moved to chiplets: several small high-yielding dies packaged together.
5. The relationship has weakened in the last decade, because leading-edge wafers now cost far more, thanks to extreme ultraviolet lithography tools and masks.
6. So density still improves, but cost per transistor improves much less than it used to, and at some nodes it may not improve at all.
7. The honest version: “transistors keep getting cheaper” was true without qualification until roughly 2012. Since then it depends on the node, the volume and who is doing the accounting.

TECHNICAL4.11.5 the engineer’s version#

1. Die cost is approximately wafer cost divided by (gross die per wafer times yield).
2. Yield follows a negative binomial model: Y = (1 + (D0 times A) divided by alpha) raised to the power minus alpha, where D0 is defect density per square centimetre, A is die area and alpha is a clustering factor.
3. Worked figures: at D0 of 0.1 defects per square centimetre and alpha of 3, a 100 square millimetre die yields about 90 percent, while a 600 square millimetre die yields about 42 percent. That yield curve, not physics, is why reticle-limit dies cost what they do.

4. These figures are approximate and vary by customer, volume and contract. Foundry pricing is confidential, so all public numbers are estimates.
5. Non-recurring engineering cost is now the dominant barrier to entry. That is why only a handful of companies design at the leading node and everything else stays on mature 28 nanometre and 16 nanometre processes.
6. The consequence for a software engineer: compute is cheap and engineer-hours are expensive, so the industry trades transistors for productivity. That trade is why abstraction layers keep multiplying.
7. Established fact: cost per transistor fell by orders of magnitude from 1960 to about 2012. Active debate: whether it still falls at the leading edge. Marketing claim: any single cost-per-transistor number offered without stating node, volume and yield assumptions.

WORDS4.11.6 remember these#

1. Cost per transistor — what one switch costs you — die cost divided by transistor count, the metric Moore’s 1965 paper was actually about.
2. Yield — the fraction of chips that work — the proportion of die on a wafer passing test, modelled against defect density and die area.
3. Defect density — how dirty the process is — D0, defects per square centimetre, around 0.1 or below for a mature leading process.
4. NRE — the one-off cost before you make any chips — non-recurring engineering cost, covering design, verification and mask sets.
5. Chiplet — several small dies packaged as one — a partitioning strategy trading packaging complexity for much better yield.

4.98 Common wrong ideas#

1. Wrong: a transistor is a tiny mechanical switch. Right: nothing moves. A voltage or current changes how many charge carriers are available in a region, and that changes its conductivity.
2. Wrong: N-type silicon is negatively charged and P-type is positively charged. Right: both are electrically neutral. The letters name the majority carrier, not a net charge.
3. Wrong: a hole is a real positive particle. Right: it is a missing electron in a bond. The physics lets us treat it exactly as a positive particle, which is why the model is used, but nothing positive is moving.
4. Wrong: the gate of a MOSFET draws current to control the channel. Right: the gate is insulated and draws only a tiny tunnelling leakage. That is the whole reason CMOS logic can idle cheaply.
5. Wrong: saturation means the same thing in a BJT and a MOSFET. Right: BJT saturation means fully on with a low voltage drop. MOSFET saturation means pinched off with a nearly constant current.
6. Wrong: CMOS uses no power when idle. Right: it uses very little dynamic power when idle, but leakage is paid continuously, and since about the 90 nanometre generation it has been a major share of total power.
7. Wrong: Moore’s Law says computers get twice as fast every 18 months. Right: Moore’s 1965 statement was about components per chip at minimum cost, revised in 1975 to a two-year doubling. The 18-month performance version came from David House at Intel.
8. Wrong: clock speeds stopped rising because we ran out of transistor speed. Right: they stopped because power density stopped being constant when Dennard scaling ended, so faster clocks needed more voltage and produced unmanageable heat.
9. Wrong: a “3 nanometre” process has 3 nanometre transistors. Right: node names have been marketing labels since roughly 2011. No feature measures the node name. Use contacted poly pitch if you want a real number.
10. Wrong: Shockley invented the transistor. Right: Bardeen and Brattain built the first working device in December 1947 and are named on its patent. Shockley invented the later junction transistor. All three shared the 1956 Nobel Prize.

4.99 Chapter summary in 20 lines#

1. A computer needs an electrically controlled switch, and the transistor is the best one ever found.
2. Relays worked but had to physically move, so they were slow. Zuse’s Z3 of 1941 used about 2,600 of them at a few hertz.
3. Vacuum tubes were about a thousand times faster, but needed hot filaments, burned enormous power and failed constantly. ENIAC used about 17,468 of them and drew 150 kilowatts.
4. Pure silicon barely conducts, because every outer electron is locked into a bond.
5. Adding phosphorus or arsenic, with five outer electrons, gives spare electrons and makes N-type silicon.
6. Adding boron, with three outer electrons, leaves gaps called holes and makes P-type silicon. A hole is an absence that moves and behaves as a positive carrier.
7. One dopant atom per five million silicon atoms changes conductivity about a million-fold. That sensitivity is why purity matters so much.
8. Joining N and P material makes a depletion region and a built-in voltage of about 0.7 volts. That is a diode: easy one way, blocked the other.
9. Bardeen and Brattain made the first working transistor on 16 December 1947 at Bell Labs, announced on 30 June 1948, using germanium and two gold contacts.
10. Shockley, left off that patent, conceived the junction transistor in January 1948. It was working by 1951. All three shared the 1956 Nobel Prize.
11. The bipolar junction transistor uses a thin base to let a small base current control a collector current 100 to 300 times larger.
12. It burns power continuously, because base current can never stop while the device is on. That cost ruled it out for large digital chips.
13. The MOSFET, demonstrated by Atalla and Kahng at Bell Labs in 1959 and 1960, controls a channel through an insulator using an electric field alone.
14. Its gate draws essentially no current, so holding it on is free. Above the threshold voltage the surface inverts and a channel forms.
15. CMOS, invented by Wanlass and Sah at Fairchild in 1963, pairs an NMOS with a PMOS so exactly one is on in each steady state, leaving no path from supply to ground.
16. Dynamic power is alpha C V squared f. A billion nodes at 0.5 femtofarads, 1 volt, 3 gigahertz and 5 percent activity gives about 75 watts.
17. The same device is a switch at the flat ends of its transfer curve and an amplifier on the steep cliff between them.
18. Shapes changed because the gate lost control of short channels: planar until 2011, FinFET from Intel’s 22 nanometre process in 2012, and gate-all-around nanosheet from Samsung in 2022 and TSMC and Intel in 2025.
19. Moore’s 1965 observation was about components per chip at minimum cost, revised to two years in 1975. Dennard scaling ended around 2005, power density began rising, and cores multiplied instead of clock speeds.
20. The real story is price: from roughly one dollar per transistor in 1960 to a few billionths of a dollar today. Everything else in this book rests on that.